Comment # 23 on bug 126 from Jens Bauer

(In reply to Johannes Pfau from comment #22)
> The volatileLoad/Store intrinsics will have to suffice.

Are these guaranteed to be in the specified order for volatileLoad/Store,
assuming a, b, c and d are different memory locations:

  read a
  write b
  read c
  read d

-Or would the compiler be able to mess up the order ?
I believe it's important to be able to keep the order exactly, so that you can
transfer data using several ports.

Simple (pseudo-code) example: SWD protocol

  SWDIO_DIR = 0;   /* data direction = input */
  SWCLK = 0;       /* clock pin low */
  i = SWDIO;       /* read data */
  SWCLK = 1;       /* clock pin high */
  SWDIO_DIR = 1;   /* data direction = output */
  SWDIO = o;       /* write bit 'o' */
  SWCLK = 0;       /* clock pin low */
  cast(void)SWDIO; /* read value but throw it away. (this delay is required) */
  SWCLK = 1;       /* clock pin high */

... A much more advanced example would be to have multiple clock pins and
multiple ports where we read/write many bits on each port.