Hi, maybe this is a stupid question but I don't made it yet to solve it ;-)) I have used MAKEDEP to get a list of dependenciers and have setup the following makefile:

.SUFFIXES : .exe .obj .asm .c .cpp .cxx .res .rc

# $* contains the name of the target file without an extension

.cpp.obj :
 sc -c $*.cpp

.cc.obj :
 sc -c $<.cc

# $** Dull list of dependents of the current target.

.obj.exe :
 sc $**

devinf.obj : devinf.cc devinf.h parser.h parser_tree.h syncml.h config.h SMLFlattener.h namespace.h

The prolem is that I get an error message: "don't know how to make config.h". Hmm... I though using the *.cc syntax will of course skip the .h files. What do I need to change?
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Robert M. Münch
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Hi, just forget it. I solved it. config.h was missing :-|| in the directory.
(Maybe a message: FILE not found would help here ;-))

Further the $*.cpp and $<.cc syntax is wrong as this will append the suffix to the current filename and doesn't filter it.

And of course .cc was missing from the .SUFFIXES deritive.

Well lots of errors in one posting... Robert