Thread overview | ||||||
---|---|---|---|---|---|---|
|
September 17, 2008 Revised CPUID/cache info - for review | ||||
---|---|---|---|---|
| ||||
Attachments: | The attached code is a revision of my cache detection code, and also serves as a replacement for std.cpuid. With the 'toString' function removed, it should also be suitable for Tango, as it has no dependencies and generates no heap activity. It fixes several problems with std.cpuid. Most importantly, it works for non-Intel/non-AMD X86 processors (yes, they do exist), and has a reasonable degree of future-proofing. I've removed some bad-practice functions (eg, you should NEVER test if the vendor is Intel) and replaced them with more appropriate ones. I've included stubs for PowerPC and Sparc, and most of the logic should also work with Itanium. But I don't have much free time, and the code is rather messy. Please confirm that it works on your system. If anyone has the time to tidy it up, that would be most appreciated. -Don |
September 18, 2008 Re: Revised CPUID/cache info - for review | ||||
---|---|---|---|---|
| ||||
Posted in reply to Don Attachments: | cache.d output: Vendor string: GenuineIntel Processor string: Intel(R) Pentium(R) M processor 1.70GHz Signature: Family = 6 Model = D Stepping = 6 Features: MMX SSE SSE2 FXSR Multithreading: 1 cores / 1 threads Data caches per CPU: L1 ways = 8 linesize = 64 size = 32K L2 ways = 8 linesize = 64 size = 2048K ---------------------------- Compiler is dmd v2.019. I have to change 3 lines to successful compile. All of them are char[] -> string (invariant) Line 444 Line 603 Line 607 ------------------------- Here is cpu-z dump: |
September 23, 2008 Re: Revised CPUID/cache info - for review | ||||
---|---|---|---|---|
| ||||
Posted in reply to Don | Don wrote: > The attached code is a revision of my cache detection code, and also serves as a replacement for std.cpuid. > With the 'toString' function removed, it should also be suitable for Tango, as it has no dependencies and generates no heap activity. > > It fixes several problems with std.cpuid. Most importantly, it works for non-Intel/non-AMD X86 processors (yes, they do exist), and has a reasonable degree of future-proofing. > I've removed some bad-practice functions (eg, you should NEVER test if the vendor is Intel) and replaced them with more appropriate ones. > > I've included stubs for PowerPC and Sparc, and most of the logic should also work with Itanium. > > But I don't have much free time, and the code is rather messy. > Please confirm that it works on your system. If anyone has the time to tidy it up, that would be most appreciated. > > -Don > (Didn't notice you had this new cache.d version in my previous post) Vendor string: AuthenticAMD Processor string: AMD Athlon(tm) 64 X2 Dual Core Processor 5000+ Signature: Family = F Model = 6B Stepping = 2 Features: MMX SSE SSE2 SSE3 3DNow! 3DNow!+ MMX+ X86-64 FXSR Multithreading: 2 cores / 2 threads Data caches per CPU: L1 ways = 2 linesize = 64 size = 64K L2 ways = 16 linesize = 64 size = 512K -- Bruno Medeiros - Software Developer, MSc. in CS/E graduate http://www.prowiki.org/wiki4d/wiki.cgi?BrunoMedeiros#D |
September 23, 2008 Re: Revised CPUID/cache info - for review | ||||
---|---|---|---|---|
| ||||
Posted in reply to Don | No time to tidy, but I can confirm that it works: Vendor string: GenuineIntel Processor string: Intel(R) Core(TM)2 CPU T7600 @ 2.33GHz Signature: Family = 6 Model = F Stepping = 6 Features: MMX SSE SSE2 SSE3 FXSR Multithreading: 1 cores / 1 threads Data caches per CPU: L1 ways = 8 linesize = 64 size = 32K L2 ways = 16 linesize = 64 size = 4096K |
Copyright © 1999-2021 by the D Language Foundation