https://issues.dlang.org/show_bug.cgi?id=20118

          Issue ID: 20118
           Summary: rt/trace: rdtsc is unordered without preceding memory
                    barrie
           Product: D
           Version: D2
          Hardware: x86_64
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P1
         Component: druntime
          Assignee: nobody@puremagic.com
          Reporter: kubo39@gmail.com

RDTSC is not ordered on Intel and AMD CPUs without preceding memory barrier, and worse, the results can be non-monotonic if compared on different processors.

The intel SDM says lfence;rdtsc causes all previous instrusctions to complete before the tsc read, and AMD APM says to use mfence;rdtsc to do same thing. This is what GNU/Linux kernel does on its rdtsc_ordered function.

* https://github.com/torvalds/linux/blob/03b9730b769fc4d87e40f6104f4c5b2e43889f19/arch/x86/include/asm/msr.h#L130-L154

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