July 15, 2019 [Issue 20055] New: 128 byte-alignment cache padding for AlignedSpinLock on x86_64? | ||||
---|---|---|---|---|
| ||||
https://issues.dlang.org/show_bug.cgi?id=20055 Issue ID: 20055 Summary: 128 byte-alignment cache padding for AlignedSpinLock on x86_64? Product: D Version: D2 Hardware: x86_64 OS: All Status: NEW Severity: enhancement Priority: P1 Component: druntime Assignee: nobody@puremagic.com Reporter: kubo39@gmail.com Accroding to IntelĀ® 64 and IA-32 Architectures Optimization Reference Manual https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf > 2.3.5.4 Data Prefetching > Spatial Prefetcher: This prefetcher strives to complete every cache line fetched to the L2 cache with the pair line that completes it to a 128-byte aligned chunk. Maybe it's better to use 128-byte alignment for core.internal.spinlock.AlignedSpinLock on x86_64? -- |
Copyright © 1999-2021 by the D Language Foundation