On Jan 15, 2010, at 5:44 AM, Robert Jacques wrote:
> 
> From wikipedia:
> "Early AMD64 processors lacked the CMPXCHG16B instruction, which is an extension of the CMPXCHG8B instruction present on most post-486 processors. Similar to CMPXCHG8B, CMPXCHG16B allows for atomic operations on 128-bit double quadword (or oword) data types. This is useful for parallel algorithms that use compare and swap on data larger than the size of a pointer, common in lock-free and wait-free algorithms. Without CMPXCHG16B one must use workarounds, such as a critical section or alternative lock-free approaches"

Oops, you're right.  The problem was cx16, not cx8.  Either way, dwcas isn't reliably available anywhere but x86.

I was asking mostly about 64-bit atomic assigns (not CAS), i.e. long assignments. I take it we can't assume they are atomic?

Andrei

Sean Kelly wrote:
> On Jan 15, 2010, at 5:44 AM, Robert Jacques wrote:
>> From wikipedia:
>> "Early AMD64 processors lacked the CMPXCHG16B instruction, which is an extension of the CMPXCHG8B instruction present on most post-486 processors. Similar to CMPXCHG8B, CMPXCHG16B allows for atomic operations on 128-bit double quadword (or oword) data types. This is useful for parallel algorithms that use compare and swap on data larger than the size of a pointer, common in lock-free and wait-free algorithms. Without CMPXCHG16B one must use workarounds, such as a critical section or alternative lock-free approaches"
> 
> Oops, you're right.  The problem was cx16, not cx8.  Either way, dwcas isn't reliably available anywhere but x86.
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> dmd-concurrency at puremagic.com
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On Fri, 15 Jan 2010, Sean Kelly wrote:

> On Jan 14, 2010, at 7:20 PM, Andrei Alexandrescu wrote:
> > 
> > Speaking of which: is it reasonable to assume that all 32-bit modern architectures have a 64-bit atomic assign? How about 64-bit atomic CAS?
> 
> For x86, I think this is reasonable today.  I recall there being an issue a while back with some CPUs (I can't recall if they were from Intel or AMD) that were missing this instruction, but I think those days are gone.  Here's a page about Windows and 8 byte CAS I ran across that seems relevant:
> 
> http://www.geoffchappell.com/viewer.htm?doc=studies/windows/km/cpu/cx8.htm

I'd have to go find the, but for my work environment, there's generations of processors still in active use that don't support 2x32bit atomic word stores.  Those processors are probably about 5 years old at this point (again, from memory -- certainly less than 10).


I don't think making the assumption that they're always available is viable.  We're trying to run on all 32 bit platforms, right?

Later,
Brad

On Jan 15, 2010, at 12:54 PM, Brad Roberts wrote:

> On Fri, 15 Jan 2010, Sean Kelly wrote:
> 
>> On Jan 14, 2010, at 7:20 PM, Andrei Alexandrescu wrote:
>>> 
>>> Speaking of which: is it reasonable to assume that all 32-bit modern architectures have a 64-bit atomic assign? How about 64-bit atomic CAS?
>> 
>> For x86, I think this is reasonable today.  I recall there being an issue a while back with some CPUs (I can't recall if they were from Intel or AMD) that were missing this instruction, but I think those days are gone.  Here's a page about Windows and 8 byte CAS I ran across that seems relevant:
>> 
>> http://www.geoffchappell.com/viewer.htm?doc=studies/windows/km/cpu/cx8.htm
> 
> I'd have to go find the, but for my work environment, there's generations of processors still in active use that don't support 2x32bit atomic word stores.  Those processors are probably about 5 years old at this point (again, from memory -- certainly less than 10).
> 
> 
> I don't think making the assumption that they're always available is viable.  We're trying to run on all 32 bit platforms, right?

Maybe not all, but certainly all recent ones.

The two options for a LOCK assign on x86 are CAS and XCHG.  And unfortunately, the only one available for more than the bus width is CAS.

On Jan 15, 2010, at 10:18 AM, Andrei Alexandrescu wrote:

> I was asking mostly about 64-bit atomic assigns (not CAS), i.e. long assignments. I take it we can't assume they are atomic?
> 
> Andrei
> 
> Sean Kelly wrote:
>> On Jan 15, 2010, at 5:44 AM, Robert Jacques wrote:
>>> From wikipedia:
>>> "Early AMD64 processors lacked the CMPXCHG16B instruction, which is an extension of the CMPXCHG8B instruction present on most post-486 processors. Similar to CMPXCHG8B, CMPXCHG16B allows for atomic operations on 128-bit double quadword (or oword) data types. This is useful for parallel algorithms that use compare and swap on data larger than the size of a pointer, common in lock-free and wait-free algorithms. Without CMPXCHG16B one must use workarounds, such as a critical section or alternative lock-free approaches"
>> Oops, you're right.  The problem was cx16, not cx8.  Either way, dwcas isn't reliably available anywhere but x86.
>> _______________________________________________
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>> dmd-concurrency at puremagic.com
>> http://lists.puremagic.com/mailman/listinfo/dmd-concurrency
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> dmd-concurrency at puremagic.com
> http://lists.puremagic.com/mailman/listinfo/dmd-concurrency

Well no problem. Atomic assign can be trivially implemented with CAS:

shared long assignThis;
shared long toThis;
shared long dummy;
do dummy = toThis; while (!cas(&toThis, dummy, assignThis));


Andrei

Sean Kelly wrote:
> The two options for a LOCK assign on x86 are CAS and XCHG.  And unfortunately, the only one available for more than the bus width is CAS.
> 
> On Jan 15, 2010, at 10:18 AM, Andrei Alexandrescu wrote:
> 
>> I was asking mostly about 64-bit atomic assigns (not CAS), i.e. long assignments. I take it we can't assume they are atomic?
>>
>> Andrei
>>
>> Sean Kelly wrote:
>>> On Jan 15, 2010, at 5:44 AM, Robert Jacques wrote:
>>>> From wikipedia:
>>>> "Early AMD64 processors lacked the CMPXCHG16B instruction, which is an extension of the CMPXCHG8B instruction present on most post-486 processors. Similar to CMPXCHG8B, CMPXCHG16B allows for atomic operations on 128-bit double quadword (or oword) data types. This is useful for parallel algorithms that use compare and swap on data larger than the size of a pointer, common in lock-free and wait-free algorithms. Without CMPXCHG16B one must use workarounds, such as a critical section or alternative lock-free approaches"
>>> Oops, you're right.  The problem was cx16, not cx8.  Either way, dwcas isn't reliably available anywhere but x86.
>>> _______________________________________________
>>> dmd-concurrency mailing list
>>> dmd-concurrency at puremagic.com
>>> http://lists.puremagic.com/mailman/listinfo/dmd-concurrency
>> _______________________________________________
>> dmd-concurrency mailing list
>> dmd-concurrency at puremagic.com
>> http://lists.puremagic.com/mailman/listinfo/dmd-concurrency
> 
> _______________________________________________
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