http://d.puremagic.com/issues/show_bug.cgi?id=6829



--- Comment #30 from bearophile_hugs@eml.cc 2013-07-13 02:37:33 PDT ---
(In reply to comment #28)

> Ack, the example is bad. This one generates rol/ror:

For normal D programmers it's easy to write D "rotation" code that the D compiler doesn't recognize. So here I have proposed to add two standard rol/ror template functions to core.bitop that all D programmers can use safely and all D compilers can optimize well.

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--- Comment #31 from hsteoh@quickfur.ath.cx 2013-07-13 10:25:27 PDT ---
I still can't get it to work. I copied Walter's code exactly, compiled with dmd -O (from DMD git HEAD) and here's the disassembly:

0000000000416854 <_D4test4testFiZv>:
  416854:       55                      push   %rbp
  416855:       48 8b ec                mov    %rsp,%rbp
  416858:       48 83 ec 20             sub    $0x20,%rsp
  41685c:       53                      push   %rbx
  41685d:       41 54                   push   %r12
  41685f:       89 7d f8                mov    %edi,-0x8(%rbp)
  416862:       41 bc 07 00 00 00       mov    $0x7,%r12d
  416868:       48 89 f9                mov    %rdi,%rcx
  41686b:       41 d3 ec                shr    %cl,%r12d
  41686e:       b8 07 00 00 00          mov    $0x7,%eax
  416873:       48 ba 20 00 00 00 00    movabs $0x20,%rdx
  41687a:       00 00 00
  41687d:       48 63 d9                movslq %ecx,%rbx
  416880:       48 2b d3                sub    %rbx,%rdx
  416883:       48 89 d1                mov    %rdx,%rcx
  416886:       d3 e0                   shl    %cl,%eax
  416888:       44 0b e0                or     %eax,%r12d
  41688b:       41 81 fc 03 00 00 80    cmp    $0x80000003,%r12d
  416892:       48 89 8d e8 ff ff ff    mov    %rcx,-0x18(%rbp)
  416899:       74 0a                   je     4168a5 <_D4test4testFiZv+0x51>
  41689b:       bf 06 00 00 00          mov    $0x6,%edi
  4168a0:       e8 37 00 00 00          callq  4168dc <_D4test8__assertFiZv>
  4168a5:       41 8b c4                mov    %r12d,%eax
  4168a8:       8b 4d f8                mov    -0x8(%rbp),%ecx
  4168ab:       d3 e0                   shl    %cl,%eax
  4168ad:       41 8b d4                mov    %r12d,%edx
  4168b0:       48 8b 8d e8 ff ff ff    mov    -0x18(%rbp),%rcx
  4168b7:       d3 ea                   shr    %cl,%edx
  4168b9:       0b c2                   or     %edx,%eax
  4168bb:       83 f8 07                cmp    $0x7,%eax
  4168be:       74 0a                   je     4168ca <_D4test4testFiZv+0x76>
  4168c0:       bf 08 00 00 00          mov    $0x8,%edi
  4168c5:       e8 12 00 00 00          callq  4168dc <_D4test8__assertFiZv>
  4168ca:       41 5c                   pop    %r12
  4168cc:       5b                      pop    %rbx
  4168cd:       48 8b e5                mov    %rbp,%rsp
  4168d0:       5d                      pop    %rbp
  4168d1:       c3                      retq


I don't understand what I'm doing wrong. Is this a platform-specific issue? I'm running Linux/x86_64.

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--- Comment #32 from Walter Bright <bugzilla@digitalmars.com> 2013-07-13 12:54:15 PDT ---
(In reply to comment #31)
> I don't understand what I'm doing wrong. Is this a platform-specific issue? I'm running Linux/x86_64.

It works with 32 bit code generation, not with 64. I didn't realize that. I'll look into fixing it.

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--- Comment #33 from hsteoh@quickfur.ath.cx 2013-07-13 14:27:53 PDT ---
Interesting. Running dmd -m32 -O works, produces the rotate instructions.

For some reason, I still can't coax gdc to do this. I've tried all combinations of -O, -O2, -O3 and -m32 , -m64, and it still only produces shift + bitwise OR. Any clues, Iain? :)

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--- Comment #34 from Iain Buclaw <ibuclaw@ubuntu.com> 2013-07-14 02:47:24 PDT ---
(In reply to comment #33)
> Interesting. Running dmd -m32 -O works, produces the rotate instructions.
> 
> For some reason, I still can't coax gdc to do this. I've tried all combinations of -O, -O2, -O3 and -m32 , -m64, and it still only produces shift + bitwise OR. Any clues, Iain? :)

Works for me (gcc vanilla development) - so I'm shrugging my shoulders on this.

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--- Comment #35 from hsteoh@quickfur.ath.cx 2013-07-14 07:45:05 PDT ---
Interestingly, translating the code into C and compiling with gcc 4.8.1 does produce the rotate instructions. But compiling the D version with gdc 4.8 doesn't. I've no idea why.

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--- Comment #36 from Iain Buclaw <ibuclaw@ubuntu.com> 2013-07-14 08:10:23 PDT ---
(In reply to comment #35)
> Interestingly, translating the code into C and compiling with gcc 4.8.1 does produce the rotate instructions. But compiling the D version with gdc 4.8 doesn't. I've no idea why.

You can look at output of -fdump-tree-gimple and compare gcc to gdc generated code.

But there should be no difference. :)

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--- Comment #37 from Iain Buclaw <ibuclaw@ubuntu.com> 2013-07-14 08:38:50 PDT ---
(In reply to comment #36)
> (In reply to comment #35)
> > Interestingly, translating the code into C and compiling with gcc 4.8.1 does produce the rotate instructions. But compiling the D version with gdc 4.8 doesn't. I've no idea why.
> 
> You can look at output of -fdump-tree-gimple and compare gcc to gdc generated code.
> 
> But there should be no difference. :)

gdc 4.9.0 20130707 - produces rol/ror instructions.
gdc 4.9.0 20130616 - produces rol/ror instructions.
gdc 4.9.0 20130505 - produces shl/shr instructions.


Related commits between 10/05 - 14/05.

http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=198770 http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=198823 http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=198864

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--- Comment #38 from bearophile_hugs@eml.cc 2013-07-14 09:10:08 PDT ---
(In reply to comment #37)

> gdc 4.9.0 20130707 - produces rol/ror instructions.
> gdc 4.9.0 20130616 - produces rol/ror instructions.
> gdc 4.9.0 20130505 - produces shl/shr instructions.

I am changing my mind, maybe now I want rol/ror _intrinsics_ in core.bitop... :-)

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--- Comment #39 from Iain Buclaw <ibuclaw@ubuntu.com> 2013-07-14 10:28:05 PDT ---
(In reply to comment #38)
> (In reply to comment #37)
> 
> > gdc 4.9.0 20130707 - produces rol/ror instructions.
> > gdc 4.9.0 20130616 - produces rol/ror instructions.
> > gdc 4.9.0 20130505 - produces shl/shr instructions.
> 
> I am changing my mind, maybe now I want rol/ror _intrinsics_ in core.bitop... :-)

core.bitop might be a good idea... then I could map the functions to gcc's builtin lrotate and rrotate expressions. :o)

Slightly off the mark, but could also do vector rotate intrinsics too...

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