http://d.puremagic.com/issues/show_bug.cgi?id=9813

           Summary: Signalling NaN initialization does not always work
                    correctly on x86
           Product: D
           Version: D1 & D2
          Platform: All
        OS/Version: All
            Status: NEW
          Severity: normal
          Priority: P2
         Component: DMD
        AssignedTo: nobody@puremagic.com
        ReportedBy: clugdbug@yahoo.com.au


--- Comment #0 from Don <clugdbug@yahoo.com.au> 2013-03-25 08:56:13 PDT ---
This code should not raise the floating point 'invalid' flag.
---
void foo()
{
     double x;
     x = 2;
     real y;
     y = 7;
     float z;
     z = 4;
}
---
Here is the generated code for 32 bits:

        push    EBP
        mov    EBP,ESP
        sub    ESP,018h
        fld    qword ptr FLAT:.rodata[08h]     // load SNAN - bad!
        fstp    qword ptr -018h[EBP]
        fld    qword ptr FLAT:.rodata[019h]
        fstp    qword ptr -018h[EBP]
        fld    tbyte ptr FLAT:.rodata[02Ah]
        fstp    tbyte ptr -010h[EBP]
        mov    word ptr -6[EBP],0
        fld    tbyte ptr FLAT:.rodata[045h]
        fstp    tbyte ptr -010h[EBP]
        mov    word ptr -6[EBP],0
        fld    float ptr FLAT:.rodata[060h]
        fstp    float ptr -4[EBP]
        fld    float ptr FLAT:.rodata[06Dh]
        fstp    float ptr -4[EBP]
        leave
        ret

The problem is, that the code first assigns SNAN to the variables *by loading them through the floating point unit*. This makes them trigger an INVALID exception. For this scheme to work, the floating point values would need to be loaded by integer operations.

-- 
Configure issuemail: http://d.puremagic.com/issues/userprefs.cgi?tab=email
------- You are receiving this mail because: -------

http://d.puremagic.com/issues/show_bug.cgi?id=9813



--- Comment #1 from Don <clugdbug@yahoo.com.au> 2013-03-25 09:01:10 PDT ---
An oddity about this, is that Intel processors will not raise the INVALID exception when initializing 80-bit reals. That is the one case where the scheme works correctly. It fails on AMD for all floating-point sizes.

This is a barely-documented difference between Intel and AMD processors.

-- 
Configure issuemail: http://d.puremagic.com/issues/userprefs.cgi?tab=email
------- You are receiving this mail because: -------

http://d.puremagic.com/issues/show_bug.cgi?id=9813


Walter Bright <bugzilla@digitalmars.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |bugzilla@digitalmars.com


--- Comment #2 from Walter Bright <bugzilla@digitalmars.com> 2013-03-25 14:52:53 PDT ---
Given the erratic and frankly bad support for signalling NaNs in the hardware, my inclination is to just drop support for them.

-- 
Configure issuemail: http://d.puremagic.com/issues/userprefs.cgi?tab=email
------- You are receiving this mail because: -------

http://d.puremagic.com/issues/show_bug.cgi?id=9813


Andrej Mitrovic <andrej.mitrovich@gmail.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |andrej.mitrovich@gmail.com


--- Comment #3 from Andrej Mitrovic <andrej.mitrovich@gmail.com> 2013-03-25 15:00:33 PDT ---
Also relevant: Issue 6303

-- 
Configure issuemail: http://d.puremagic.com/issues/userprefs.cgi?tab=email
------- You are receiving this mail because: -------

http://d.puremagic.com/issues/show_bug.cgi?id=9813



--- Comment #4 from Don <clugdbug@yahoo.com.au> 2013-07-26 07:47:40 PDT ---
*** Issue 6303 has been marked as a duplicate of this issue. ***

-- 
Configure issuemail: http://d.puremagic.com/issues/userprefs.cgi?tab=email
------- You are receiving this mail because: -------