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| Posted by Walter Bright in reply to H. S. Teoh | PermalinkReply |
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Walter Bright
Posted in reply to H. S. Teoh
| On 5/19/2022 1:24 PM, H. S. Teoh wrote:
> IME, gcc and ldc2 are well able to convert the above ?: expression into
> the latter, without uglifying the code. Why are we promoting (or even
> allowing) this kind of ugly code just because dmd's optimizer is so
> lackluster you have to manually spell things out this way?
See my reply to Steven.
BTW, consider auto-vectorizing compilers. A common characteristic of them is that sometimes a loop looks like it should be vectorized, but the compiler didn't, for reasons that are opaque to users. The compiler then substitutes a slow emulation to give the *appearance* of being vectorized.
The only way to tell what is happening is to dump the generate assembler. This is especially troublesome you're attempting to write vector code that is portable among various SIMD instruction sets. It doesn't scale, at all.
This is based on many conversations about this with Manu Evans, who's career was based on writing vector code. Manu has been very influential in the design of D's vector semantics.
Hence D's approach is different. You can write vector code in D. If it won't compile to the target instruction set, it doesn't replace it with emulation. It signals an error. Thus, the user knows if he writes vector code, he gets vector code. It makes it easy for him to use versioning to adjust the shape of the expressions to line up with the vector capabilities of each target.
To sum up, if you want a particular instruction mix in the output stream, a systems programming language must enable expression of that desired mix. It must not rely on undocumented and inconsistent compiler transformations.
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