Is there a particular reason explaining why mov reg,0 is used and not xor reg,reg ?
(or even and reg, 0)

for example here:

https://github.com/D-Programming-Language/druntime/blob/master/src/core/atomic.d#L1009

It seems that in Go too mov is used:
https://github.com/golang/go/blob/0104a31b8fbcbe52728a08867b26415d282c35d2/src/runtime/internal/atomic/asm_amd64p32.s#L15

On 04/10/2016 04:00 AM, darat wrote:
> Is there a particular reason explaining why mov reg,0 is used and not
> xor reg,reg ?
> (or even and reg, 0)
>
> for example here:
>
> https://github.com/D-Programming-Language/druntime/blob/master/src/core/atomic.d#L1009
>
>
> It seems that in Go too mov is used:
> https://github.com/golang/go/blob/0104a31b8fbcbe52728a08867b26415d282c35d2/src/runtime/internal/atomic/asm_amd64p32.s#L15
>
>
>
>

I don't know the answer but Google finds interesting discussions about that:


https://www.google.com/search?q=mov+0+versus+xor+cycles&ie=utf-8&oe=utf-8#q=mov+0+versus+xor+cpu+cycle

Ali

On Monday, 11 April 2016 at 05:45:17 UTC, Ali Çehreli wrote:
> On 04/10/2016 04:00 AM, darat wrote:
>> Is there a particular reason explaining why mov reg,0 is used and not
>> xor reg,reg ?
> https://www.google.com/search?q=mov+0+versus+xor+cycles&ie=utf-8&oe=utf-8#q=mov+0+versus+xor+cpu+cycle
>
> Ali

I've read them all before posting here. Nothing answers the question. The only clue is maybe that xor modifies the EFLAG register, but since inline asm is not inlined (there's always a CALL) I'm not 100% sure this is relevant.

https://randomascii.wordpress.com/2012/12/29/the-surprising-subtleties-of-zeroing-a-register/
> But there was at least one out-of-order design that did not recognize xor reg, reg as a special case: the Pentium Pro. The Intel Optimization manuals for the Pentium Pro recommended “mov” to zero a register.