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June 24, 2010 [dmd-internals] dmd commit, revision 558 | ||||
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dmd commit, revision 558 user: walter msg: 64 http://www.dsource.org/projects/dmd/changeset/558 |
June 24, 2010 [dmd-internals] dmd commit, revision 558 | ||||
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Posted in reply to dsource.org | I saw this commit adds some XMM0..XMM7 code. What about XMM8..XMM15? AMD introduced these 8 additional registers with their SSE2 implementation in 2003 and Intel adopted it with Intel64 in 2004 already. |
June 24, 2010 [dmd-internals] dmd commit, revision 558 | ||||
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Posted in reply to dsource.org | 568 #define REGMAX 17 // registers are numbered 0..10 568 #define REGMAX 29 // registers are numbered 0..10 It looks like this comment has been out of date for several revisions... Time to delete it? Sent from my iPhone On Jun 24, 2010, at 4:52 PM, "dsource.org" <noreply at dsource.org> wrote: > dmd commit, revision 558 > > > user: walter > > msg: > 64 > > http://www.dsource.org/projects/dmd/changeset/558 > > _______________________________________________ > dmd-internals mailing list > dmd-internals at puremagic.com > http://lists.puremagic.com/mailman/listinfo/dmd-internals -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.puremagic.com/pipermail/dmd-internals/attachments/20100624/2a27864a/attachment.html> |
June 24, 2010 [dmd-internals] dmd commit, revision 558 | ||||
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Posted in reply to Trass3r |
Trass3r wrote:
> I saw this commit adds some XMM0..XMM7 code.
> What about XMM8..XMM15?
> AMD introduced these 8 additional registers with their SSE2
> implementation in 2003 and Intel adopted it with Intel64 in 2004 already.
>
They won't fit in the 32 bit mask. I haven't decided how to deal with it yet.
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June 25, 2010 [dmd-internals] dmd commit, revision 558 | ||||
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Posted in reply to Walter Bright | > They won't fit in the 32 bit mask. I haven't decided how to deal with it yet.
Ah I see.
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